This invention relates to the field of integrated circuits packaged in a molded housing. More particularly, this invention relates to a method of suppressing noise (e.g. decoupling) from the voltage to ground distribution circuit in integrated circuit packages such as surface mounted leadless chip carriers.
It is well known in the field of microelectronics that high frequency operation, particularly the switching of integrated circuits (IC), can result in transient energy being coupled into the power supply circuit. It is also well known that integrated circuits are becoming more dense (more gates per unit area of silicon/or gallium arsenide), more powerful (more watts per unit area of IC chip), and faster with higher clock rate frequencies and with smaller rise times. All of these recent and continued developments make the problem of suppressing noise in the power bus (produced by a large amount of simultaneous gates switching) even more serious than in the past.
Generally, the prevention of the coupling of undesired high frequency noise or interference into the power supply for an integrated circuit is accomplished by connecting a decoupling capacitor between the power and the ground leads of the IC. Conventional methods of decoupling (noise suppression) include the use of decoupling capacitors external to the IC package, such as monolithic multilayer ceramic chip capacitors. One external connection scheme of this type which has been found to be quite successful is to mount a decoupling capacitor underneath an integrated circuit. Examples of these decoupling capacitors are found in U.S. Pat. Nos. 4,475,143, 4,502,101 and 4,748,537. These patents disclose decoupling capacitors which are particularly well suited for pin grid array and plastic leaded chip carrier packages.
Still other decoupling connection schemes are known. For example, multilayer capacitor (MLC) chips have been placed on top of pin grid array (PGA) ceramic IC packages with interconnections built-in from the surface of the PGA package down to the proper places in internal circuitry of the package. In still some other cases, schemes have been devised to incorporate a MLC chip into a specially configured IC lead frame, but due to production difficulties, this approach has not become widely accepted. Attempts have also been made to build a capacitive layer into a PGA ceramic package (and into a leadless ceramic chip carrier), by using thin layers of alumina or other adequate ceramic dielectric material. Again, this approach has not found wide acceptance.
Another approach engendered by U.S. Pat. No. 4,994,936 utilizes a flat decoupling capacitor that is attached directly to the IC lead frame and thereafter encapsulated within the molded package along with the IC chip, resulting in a decoupling scheme which is internal to the molded IC package. The capacitor is of the parallel plate type and is a thin layer of ceramic dielectric sandwiched between top and bottom conductors. The top conductor is attached to the die bar of the lead frame using an adhesive. Leads extending from the capacitors are attached to appropriate fingers of the lead frame to effect mechanical and electrical contact.
In spite of all these innovations, most decoupling capacitors are discrete MLC soldered to the main PCB near the IC package. Obviously, there continues to be a need for improved connection schemes for decoupling undesired high frequency noise from integrated circuits wherein the inductance within the decoupling loop is reduced to as low a level as possible.